? semiconductor components industries, llc, 2005 february, 2005 ? rev. 5 1 publication order number: MC14017B/d MC14017B decade counter the MC14017B is a five?stage johnson decade counter with built?in code converter. high speed operation and spike?free outputs are obtained by use of a johnson decade counter design. the ten decoded outputs are normally low, and go high only at their appropriate decimal time period. the output changes occur on the positive?going edge of the clock pulse. this part can be used in frequency division applications as well as decade counter or decimal decode display applications. features ? fully static operation ? dc clock input circuit allows slow rise times ? carry out output for cascading ? divide?by?n counting ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pin?for?pin replacement for cd4017b ? triple diode protection on all inputs ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagrams pdip?16 p suffix case 648 MC14017Bcp awlyyww soic?16 d suffix case 751b 14017b awlyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week soeiaj?16 f suffix case 966 MC14017B awlyww see detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ordering information 16 1 1 16 1 16
MC14017B http://onsemi.com 2 block diagram functional truth table (positive logic) clock decode clock enable reset output=n 0x0 n x10 n xx1 q0 0 0 n+1 x0 n x0n 1 0 n+1 x = don't care. if n < 5 carry = a1o, otherwise = a0o. clock clock enable reset 14 13 15 c out q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 3 2 4 7 10 1 5 6 9 11 12 v dd = pin 16 v ss = pin 8 logic diagram clock clock enable carry reset q5 q1 q7 q3 q9 11 7 6 2 1 12 q0 q6 q2 q3 q4 354910 14 13 15 c c d rr q q pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 c out ce clock reset v dd q8 q4 q9 q2 q0 q1 q5 v ss q3 q7 q6 c c d rr q q c c d rr q q c c d rr q q c c d rr q q
MC14017B http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) ?????????? ?????????? ???? ???? ??? ??? v ????? ????? ? 55 c ????????? ????????? 25 c ????? ????? 125 c ??? ??? ?????????? ? ???????? ? ?????????? characteristic ???? ? ?? ? ???? symbol ??? ? ? ? ??? v dd vdc ??? ? ? ? ??? min ??? ? ? ? ??? max ???? ? ?? ? ???? min ??? ? ? ? ??? typ (note 2) ???? ? ?? ? ???? max ??? ? ? ? ??? min ??? ? ? ? ??? max ??? ? ? ? ??? unit ?????????? ? ???????? ? ?????????? output voltage a0o level v in = v dd or 0 ???? ? ?? ? ???? v ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0 0 0 ???? ? ?? ? ???? 0.05 0.05 0.05 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ??? ? ? ? ??? vdc ?????????? ? ???????? ? ?????????? a1o level v in = 0 or v dd ???? ? ?? ? ???? v oh ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? e e e ???? ? ?? ? ???? 4.95 9.95 14.95 ??? ? ? ? ??? 5.0 10 15 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ??? e e e ??? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ???? ? ?? ? ? ?? ? ???? v il ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 2.25 4.50 6.75 ???? ? ?? ? ? ?? ? ???? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.5 3.0 4.0 ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) ???? ? ?? ? ? ?? ? ???? v ih ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? 2.75 5.50 8.25 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 3.5 7.0 11 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) ???? ? ?? ? ? ?? ? ???? i oh ??? ? ? ? ? ? ? ??? 5.0 5.0 10 15 ??? ? ? ? ? ? ? ??? 3.0 0.64 1.6 4.2 ??? ? ? ? ? ? ? ??? e e e e ???? ? ?? ? ? ?? ? ???? 2.4 0.51 1.3 3.4 ??? ? ? ? ? ? ? ??? 4.2 0.88 2.25 8.8 ???? ? ?? ? ? ?? ? ???? e e e e ??? ? ? ? ? ? ? ??? 1.7 0.36 0.9 2.4 ??? ? ? ? ? ? ? ??? e e e e ??? ? ? ? ? ? ? ??? madc ?????????? ? ???????? ? ? ???????? ? ?????????? (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) ???? ? ?? ? ? ?? ? ???? i ol ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 0.64 1.6 4.2 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 0.51 1.3 3.4 ??? ? ? ? ? ? ? ??? 0.88 2.25 8.8 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 0.36 0.9 2.4 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? madc ?????????? ?????????? input current ???? ???? i in ??? ??? 15 ??? ??? e ??? ??? 0.1 ???? ???? e ??? ??? 0.00001 ???? ???? 0.1 ??? ??? e ??? ??? 1.0 ??? ??? adc ?????????? ?????????? input capacitance (v in = 0) ???? ???? c in ??? ??? e ??? ??? e ??? ??? e ???? ???? e ??? ??? 5.0 ???? ???? 7.5 ??? ??? e ??? ??? e ??? ??? pf ?????????? ? ???????? ? ?????????? quiescent current (per package) ???? ? ?? ? ???? i dd ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 5.0 10 20 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0.005 0.010 0.015 ???? ? ?? ? ???? 5.0 10 20 ??? ? ? ? ??? e e e ??? ? ? ? ??? 150 300 600 ??? ? ? ? ??? adc ?????????? ? ???????? ? ? ???????? ? ? ???????? ? ?????????? total supply current (notes 3 & 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) ???? ? ?? ? ? ?? ? ? ?? ? ???? i t ??? ? ? ? ? ? ? ? ? ? ??? 5.0 10 15 ????????????????? ? ??????????????? ? ? ??????????????? ? ? ??????????????? ? ????????????????? i t = (0.27 a/khz) f + i dd i t = (0.55 a/khz) f + i dd i t = (0.83 a/khz) f + i dd ??? ? ? ? ? ? ? ? ? ? ??? adc 2. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.0011. ordering information device package shipping 2 MC14017Bcp pdip?16 500 units / rail MC14017Bcpg pdip?16 (pb?free) 500 units / rail MC14017Bd soic?16 48 units / rail MC14017Bdr2 soic?16 2500 units / tape & reel MC14017Bdr2g soic?16 (pb?free) 2500 units / tape & reel MC14017Bfel soeiaj?16 2000 units / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
MC14017B http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (note 5) (c l = 50 pf, t a = 25 c) ??????????????? ? ????????????? ? ??????????????? characteristic ????? ? ??? ? ????? symbol ???? ? ?? ? ???? v dd vdc ???? ? ?? ? ???? min ???? ? ?? ? ???? typ (note 6) ???? ? ?? ? ???? max ??? ? ? ? ??? unit ??????????????? ? ????????????? ? ??????????????? output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns ????? ? ??? ? ????? t tlh , t thl ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? e e e ???? ? ?? ? ???? 100 50 40 ???? ? ?? ? ???? 200 100 80 ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time reset to decode output t plh , t phl = (1.7 ns/pf) c l + 415 ns t plh , t phl = (0.66 ns/pf) c l + 197 ns t plh , t phl = (0.5 ns/pf) c l + 150 ns ????? ? ??? ? ? ??? ? ? ??? ? ????? t plh , t phl ???? ? ?? ? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ? ?? ? ???? 500 230 175 ???? ? ?? ? ? ?? ? ? ?? ? ???? 1000 460 350 ??? ? ? ? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time clock to c out t plh , t phl = (1.7 ns/pf) c l + 315 ns t plh , t phl = (0.66 ns/pf) c l + 142 ns t plh , t phl = (0.5 ns/pf) c l + 100 ns ????? ? ??? ? ? ??? ? ? ??? ? ????? t plh , t phl ???? ? ?? ? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ? ?? ? ???? 400 175 125 ???? ? ?? ? ? ?? ? ? ?? ? ???? 800 350 250 ??? ? ? ? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time clock to decode output t plh , t phl = (1.7 ns/pf) c l + 415 ns t plh , t phl = (0.66 ns/pf) c l + 197 ns t plh , t phl = (0.5 ns/pf) c l + 150 ns ????? ? ??? ? ? ??? ? ????? t plh , t phl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 500 230 175 ???? ? ?? ? ? ?? ? ???? 1000 460 350 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ? ????????????? ? ??????????????? turn?off delay time reset to c out t plh = (1.7 ns/pf) c l + 315 ns t plh = (0.66 ns/pf) c l + 142 ns t plh = (0.5 ns/pf) c l + 100 ns ????? ? ??? ? ? ??? ? ? ??? ? ????? t plh ???? ? ?? ? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ? ?? ? ???? 400 175 125 ???? ? ?? ? ? ?? ? ? ?? ? ???? 800 350 250 ??? ? ? ? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ??????????????? clock pulse width ????? ? ??? ? ????? t w(h) ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 250 100 75 ???? ? ?? ? ???? 125 50 35 ???? ? ?? ? ???? e e e ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? clock frequency ????? ? ??? ? ? ??? ? ????? f cl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 5.0 12 16 ???? ? ?? ? ? ?? ? ???? 2.0 5.0 6.7 ??? ? ? ? ? ? ? ??? mhz ??????????????? ? ????????????? ? ??????????????? reset pulse width ????? ? ??? ? ????? t w(h) ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 500 250 190 ???? ? ?? ? ???? 250 125 95 ???? ? ?? ? ???? e e e ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ??????????????? reset removal time ????? ? ??? ? ????? t rem ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 750 275 210 ???? ? ?? ? ???? 375 135 105 ???? ? ?? ? ???? e e e ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? clock input rise and fall time ????? ? ??? ? ? ??? ? ????? t tlh , t thl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ?????????? ? ???????? ? ? ???????? ? ?????????? no limit ??? ? ? ? ? ? ? ??? e ??????????????? ? ????????????? ? ??????????????? clock enable setup time ????? ? ??? ? ????? t su ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 350 150 115 ???? ? ?? ? ???? 175 75 52 ???? ? ?? ? ???? e e e ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ??????????????? clock enable removal time ????? ? ??? ? ????? t rem ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? 420 200 140 ???? ? ?? ? ???? 260 100 70 ???? ? ?? ? ???? e e e ??? ? ? ? ??? ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance.
MC14017B http://onsemi.com 5 figure 1. typical output source and output sink characteristics test circuit v dd v out v ss v dd v ss s1 s1 a b v ss i d external power supply clock enable reset clock c out q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 output sink drive output source drive decode outputs clock to desired outputs (s1 to b) (s1 to a) carry clock to 5 thru 9 (s1 to b) s1 to a v gs =? v dd v dd v ds =v out ? v dd v out figure 2. typical power dissipation test circuit v dd v ss i d clock enable reset clock c out q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 500 f 0.01 f ceramic pulse generator f c c l c l c l c l c l c l c l c l c l c l c l
MC14017B http://onsemi.com 6 applications information figure 3 shows a technique for extending the number of decoded output states for the MC14017B. decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). figure 3. counter expansion reset clock ce MC14017B q0 q1 q8 q9 ??? 9 decoded outputs clock first stage intermediate stages last stage reset clock ce MC14017B q0q1 q8 q9 ??? reset clock ce MC14017B q1 q8 q9 ??? 8 decoded outputs 8 decoded outputs figure 4. ac measurement definition and functional waveforms pcp ncp clock clock enable t rem reset 20 ns q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 c out t phl t phl t plh t plh t plh t plh t plh t plh t thl t thl t tlh t plh t plh t plh t tlh t plh t phl t phl t phl t phl 50% t phl t phl 90% 10% t thl t phl t thl t phl t thl t tlh t thl t phl t rem t su 20 ns 20 ns 20 ns 20 ns t plh 90% 10% 50% t tlh t tlh t tlh t tlh t tlh t thl t thl t thl t thl t phl t thl 90% 50% 10% 20 ns t plh t tlh v dd v ss v dd v ss v dd v ss v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol
MC14017B http://onsemi.com 7 package dimensions pdip?16 p suffix plastic dip package case 648?08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic?16 d suffix plastic soic package case 751b?05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
MC14017B http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj?16 f suffix plastic eiaj soic package case 966?01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MC14017B/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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